Datasheet

10. Memories
10.1 Embedded Memories
• Internal high-speed flash with Read-While-Write (RWW) capability on section of the array (Device
Variant B, C, D, and L).
• Internal high-speed RAM, single-cycle access at full speed
10.2 Physical Memory Map
The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they
are never remapped in any way, even during boot. The 32-bit physical address space is mapped as
follow:
Table 10-1. SAM D21 Physical Memory Map
(1)
Memory
Start address Size
SAMD21x18 SAMD21x17 SAMD21x16 SAMD21x15 SAMD21x16L SAMD21x15L
Internal Flash 0x00000000 256 Kbytes 128 Kbytes 64 Kbytes 32 Kbytes 64 Kbytes 32 Kbytes
Internal RWW
section
(2)
0x00400000 - 4 Kbytes 2 Kbytes 1 Kbytes 2 Kbytes 1 Kbytes
Internal SRAM 0x20000000 32 Kbytes 16 Kbytes 8 Kbytes 4 Kbytes 8 Kbytes 4 Kbytes
Peripheral Bridge A 0x40000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
Peripheral Bridge B 0x41000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
Peripheral Bridge C 0x42000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
IOBUS 0x60000000 0.5 Kbytes 0.5 Kbytes 0.5 Kbytes 0.5 Kbytes 0.5 Kbytes 0.5 Kbytes
Notes:
1. x = G, J or E.
2. Only applicable for device variants B, C, D,and L.
Table 10-2. Flash Memory Parameters
(1,2)
Device Flash size Number of pages Page size
SAMD21x18 256 Kbytes 4096 64 bytes
SAMD21x17 128 Kbytes 2048 64 bytes
SAMD21x16 64 Kbytes 1024 64 bytes
SAMD21x15 32 Kbytes 512 64 bytes
Notes:
1. x = G, J or E.
2. The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size
bits in the NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively).
Refer to NVM Parameter (PARAM) register for details.
SAM D21 Family
Memories
© 2018 Microchip Technology Inc.
Datasheet Complete
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