Datasheet

has control over the output state of the pad, as well as the ability to read the current physical pad state.
Refer to I/O Multiplexing and Considerations for details.
Device-specific configurations may cause some lines (and the corresponding Pxy pin) not to be
implemented.
Related Links
7. I/O Multiplexing and Considerations
23.5.2 Power Management
During Reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
The PORT peripheral will continue operating in any sleep mode where its source clock is running.
23.5.3 Clocks
The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Power Manager, and the
default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section in PM – Power
Manager.
The PORT requires an APB clock, which may be divided from the CPU main clock and allows the CPU to
access the registers of PORT through the high-speed matrix and the AHB/APB bridge.
The PORT also requires an AHB clock for CPU IOBUS accesses to the PORT. That AHB clock is the
internal PORT clock.
The priority of IOBUS accesses is higher than APB accesses. One clock cycle latency can be observed
on the APB access in case of concurrent PORT accesses.
Related Links
16.6.2.6 Peripheral Clock Masking
23.5.4 DMA
Not applicable.
23.5.5 Interrupts
Not applicable.
23.5.6 Events
The events of this peripheral are connected to the Event System.
Related Links
24. EVSYS – Event System
23.5.7 Debug Operation
When the CPU is halted in debug mode, this peripheral will continue normal operation.
23.5.8 Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller
(PAC).
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
Write-protection does not apply for accesses through an external debugger.
SAM D21 Family
PORT - I/O Pin Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 408