Datasheet

22.8.4 Interrupt Enable Clear

Name: INTENCLR

Offset: 0x0C

Reset: 0x00

Property: PAC Write-Protection

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes

in this register will also be reflected in the Interrupt Enable Set register (INTENSET).

Bit 7 6 5 4 3 2 1 0

ERROR READY

Access

R/W R/W

Reset 0 0

Bit 1 – ERROR Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the ERROR interrupt enable.

This bit will read as the current value of the ERROR interrupt enable.

Bit 0 – READY NVM Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the READY interrupt enable.

This bit will read as the current value of the READY interrupt enable.

SAM D21 Family

NVMCTRL – Nonvolatile Memory Controller

Datasheet Complete

DS40001882D-page 399