Datasheet

22.8.2 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x00000080
Property: PAC Write-Protection
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CACHEDIS READMODE[1:0]
Access
R/W R/W R/W
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
SLEEPPRM[1:0]
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
MANW RWS[3:0]
Access
R/W R/W R/W R/W R/W
Reset 1 0 0 0 0
Bit 18 – CACHEDIS Cache Disable
This bit is used to disable the cache.
Value Description
0
The cache is enabled
1
The cache is disabled
Bits 17:16 – READMODE[1:0] NVMCTRL Read Mode
Value Name Description
0x0
NO_MISS_PENALTY The NVM Controller (cache system) does not insert wait states on a
cache miss. Gives the best system performance.
0x1
LOW_POWER Reduces power consumption of the cache system, but inserts a wait
state each time there is a cache miss. This mode may not be relevant
if CPU performance is required, as the application will be stalled and
may lead to increased run time.
0x2
DETERMINISTIC The cache system ensures that a cache hit or miss takes the same
amount of time, determined by the number of programmed Flash wait
states. This mode can be used for real-time applications that require
deterministic execution timings.
0x3
Reserved
SAM D21 Family
NVMCTRL – Nonvolatile Memory Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 396