Datasheet

22.8.1 Control A
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection
Bit 15 14 13 12 11 10 9 8
CMDEX[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CMD[6:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bits 15:8 – CMDEX[7:0] Command Execution
When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a
value different from the key value is tried, the write will not be performed and the Programming Error bit in
the Status register (STATUS.PROGE) will be set. PROGE is also set if a previously written command is
not completed yet.
The key value must be written at the same time as CMD. If a command is issued through the APB bus on
the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then
be executed when the NVM block and the AHB bus are idle.
INTFLAG.READY must be '1' when the command is issued.
Bit 0 of the CMDEX bit group will read back as '1' until the command is issued.
Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.
Bits 6:0 – CMD[6:0] Command
These bits define the command to be executed when the CMDEX key is written.
CMD[6:0] Group
Configuration
Description
0x00-0x01 - Reserved
0x02 ER Erase Row - Erases the row addressed by the ADDR register in the
NVM main array.
0x03 - Reserved
0x04 WP Write Page - Writes the contents of the page buffer to the page
addressed by the ADDR register.
0x05 EAR Erase Auxiliary Row - Erases the auxiliary row addressed by the
ADDR register. This command can be given only when the Security
bit is not set and only to the User Configuration Row.
SAM D21 Family
NVMCTRL – Nonvolatile Memory Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 394