Datasheet

22.7 Register Summary
Offset Name Bit Pos.
0x00 CTRLA
7:0 CMD[6:0]
15:8 CMDEX[7:0]
0x02
...
0x03
Reserved
0x04 CTRLB
7:0 MANW RWS[3:0]
15:8 SLEEPPRM[1:0]
23:16 CACHEDIS READMODE[1:0]
31:24
0x08 PARAM
7:0 NVMP[7:0]
15:8 NVMP[15:8]
23:16 RWWEEP[3:0] PSZ[2:0]
31:24 RWWEEP[11:4]
0x0C INTENCLR 7:0 ERROR READY
0x0D
...
0x0F
Reserved
0x10 INTENSET 7:0 ERROR READY
0x11
...
0x13
Reserved
0x14 INTFLAG 7:0 ERROR READY
0x15
...
0x17
Reserved
0x18 STATUS
7:0 NVME LOCKE PROGE LOAD PRM
15:8 SB
0x1A
...
0x1B
Reserved
0x1C ADDR
7:0 ADDR[7:0]
15:8 ADDR[15:8]
23:16 ADDR[21:16]
31:24
0x20 LOCK
7:0 LOCK[7:0]
15:8 LOCK[15:8]
22.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
SAM D21 Family
NVMCTRL – Nonvolatile Memory Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 392