Datasheet

When the last location in the page buffer is written, the page is automatically written to NVM main
address space.
• INTFLAG.READY will be zero while programming is in progress and access through the AHB will
be stalled.
22.6.4.4 Page Buffer Clear
The page buffer is automatically set to all '1' after a page write is performed. If a partial page has been
written and it is desired to clear the contents of the page buffer, the Page Buffer Clear command can be
used.
22.6.4.5 Erase Row
Before a page can be written, the row containing that page must be erased. The Erase Row command
can be used to erase the desired row in the NVM main address space. The RWWEE Erase Row can be
used to erase the desired row in the RWWEE array. Erasing the row sets all bits to '1'. If the row resides
in a region that is locked, the erase will not be performed and the Lock Error bit in the Status register
(STATUS.LOCKE) will be set.
22.6.4.5.1 Procedure for Erase Row
• Write the address of the row to erase to ADDR. Any address within the row can be used.
• Issue an Erase Row command.
Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.
22.6.4.6 Lock and Unlock Region
These commands are used to lock and unlock regions as detailed in section 22.6.3 Region Lock Bits.
22.6.4.7 Set and Clear Power Reduction Mode
The NVM Controller and block can be taken in and out of power reduction mode through the Set and
Clear Power Reduction Mode commands. When the NVM Controller and block are in power reduction
mode, the Power Reduction Mode bit in the Status register (STATUS.PRM) is set.
22.6.5 NVM User Configuration
The NVM user configuration resides in the auxiliary space. Refer to the Physical Memory Map of the
device for calibration and auxiliary space address mapping.
The bootloader resides in the main array starting at offset zero. The allocated boot loader section is write-
protected.
Table 22-2. Boot Loader Size
BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes
0x7
(1)
None 0
0x6 2 512
0x5 4 1024
0x4 8 2048
0x3 16 4096
0x2 32 8192
0x1 64 16384
0x0 128 32768
SAM D21 Family
NVMCTRL – Nonvolatile Memory Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 390