Datasheet

22.4 Signal Description
Not applicable.
22.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described in the
following sections.
22.5.1 Power Management
The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running.
The NVMCTRL interrupts can be used to wake up the device from sleep modes.
The Power Manager will automatically put the NVM block into a low-power state when entering sleep
mode. This is based on the Control B register (CTRLB) SLEEPPRM bit setting. Refer to the 22.8.2
CTRLB. SLEEPPRM register description for more details. The NVM block goes into low-power mode
automatically when the device enters STANDBY mode regardless of SLEEPPRM. The NVM Page Buffer
is lost when the NVM goes into low power mode therefore a write command must be issued prior entering
the NVM low power mode. NVMCTRL SLEEPPRM can be disabled to avoid such loss when the CPU
goes into sleep except if the device goes into STANDBY mode for which there is no way to retain the
Page Buffer.
Related Links
16. PM – Power Manager
22.5.2 Clocks
Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus
(CLK_NVMCTRL_AHB) and the other is provided by the APB bus (CLK_NVMCTRL_APB). For higher
system frequencies, a programmable number of wait states can be used to optimize performance. When
changing the AHB bus frequency, the user must ensure that the NVM Controller is configured with the
proper number of wait states. Refer to the Electrical Characteristics for the exact number of wait states to
be used for a particular frequency range.
Related Links
37. Electrical Characteristics
22.5.3 Interrupts
The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL
interrupt requires the interrupt controller to be programmed first.
22.5.4 Debug Operation
When an external debugger forces the CPU into debug mode, the peripheral continues normal operation.
Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be
accessible. See the section on the NVMCTRL 22.6.6 Security Bit for details.
22.5.5 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC),
except the following registers:
• Interrupt Flag Status and Clear register (INTFLAG)
SAM D21 Family
NVMCTRL – Nonvolatile Memory Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 384