Datasheet
21.8.1 Control
Name: CTRL
Offset: 0x00
Reset: 0x00
Property: Write-Protected, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
ENABLE SWRST
Access
R/W R/W
Reset 0 0
Bit 1 – ENABLE Enable
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/
disabled. The value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy
bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when
the operation is complete.
Value Description
0
The EIC is disabled.
1
The EIC is enabled.
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the EIC to their initial state, and the EIC will be disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same
write operation will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value Description
0
There is no ongoing reset operation.
1
The reset operation is ongoing.
SAM D21 Family
EIC – External Interrupt Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 373