Datasheet

When an NMI is detected, the non-maskable interrupt flag in the NMI Flag Status and Clear register is set
(NMIFLAG.NMI). NMI interrupt generation is always enabled, and NMIFLAG.NMI generates an interrupt
request when set.
21.6.5 DMA Operation
Not applicable.
21.6.6 Interrupts
The EIC has the following interrupt sources:
• External interrupt pins (EXTINTx). See 21.6.2 Basic Operation.
• Non-maskable interrupt pin (NMI). See 21.6.4 Additional Features.
Each interrupt source has an associated interrupt flag. The interrupt flag in the Interrupt Flag Status and
Clear register (INTFLAG) is set when an interrupt condition occurs (NMIFLAG for NMI). Each interrupt,
except NMI, can be individually enabled by setting the corresponding bit in the Interrupt Enable Set
register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear
register (INTENCLR=1).
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the EIC
is reset. See the INTFLAG register for details on how to clear interrupt flags. The EIC has one interrupt
request line for each external interrupt (EXTINTx) and one line for NMI. The user must read the INTFLAG
(or NMIFLAG) register to determine which interrupt condition is present.
Note:
1. Interrupts must be globally enabled for interrupt requests to be generated.
2. If an external interrupts (EXTINT) is common on two or more I/O pins, only one will be active (the
first one programmed).
Related Links
7.1 Multiplexed Signals
11. Processor And Architecture
21.6.7 Events
The EIC can generate the following output events:
• External event from pin (EXTINTx).
Setting an Event Output Control register (EVCTRL.EXTINTEO) enables the corresponding output event.
Clearing this bit disables the corresponding output event. Refer to Event System for details on configuring
the Event System.
When the condition on pin EXTINTx matches the configuration in the CONFIGn register, the
corresponding event is generated, if enabled.
Related Links
24. EVSYS – Event System
21.6.8 Sleep Mode Operation
In sleep modes, an EXTINTx pin can wake up the device if the corresponding condition matches the
configuration in CONFIGy register. Writing a one to a Wake-Up Enable bit (WAKEUP.WAKEUPEN[x])
enables the wake-up from pin EXTINTx. Writing a zero to a Wake-Up Enable bit
(WAKEUP.WAKEUPEN[x]) disables the wake-up from pin EXTINTx.
SAM D21 Family
EIC – External Interrupt Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 370