Datasheet

21.4 Signal Description
Signal Name Type Description
EXTINT[15..0] Digital Input External interrupt pin
NMI Digital Input Non-maskable interrupt pin
One signal may be available on several pins.
Related Links
7. I/O Multiplexing and Considerations
21.5 Product Dependencies
In order to use this EIC, other parts of the system must be configured correctly, as described below.
21.5.1 I/O Lines
Using the EIC’s I/O lines requires the I/O pins to be configured.
Related Links
23. PORT - I/O Pin Controller
21.5.2 Power Management
All interrupts are available down to STANDBY sleep mode, but the EIC can be configured to automatically
mask some interrupts in order to prevent device wake-up.
The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC’s
interrupts can be used to wake up the device from sleep modes. Events connected to the Event System
can trigger other operations in the system without exiting sleep modes.
Related Links
16. PM – Power Manager
21.5.3 Clocks
The EIC bus clock (CLK_EIC_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_EIC_APB can be found in the Peripheral Clock Masking section in PM – Power Manager.
A generic clock (GCLK_EIC) is required to clock the peripheral. This clock must be configured and
enabled in the Generic Clock Controller before using the peripheral. Refer to GCLK – Generic Clock
Controller.
This generic clock is asynchronous to the user interface clock (CLK_EIC_APB). Due to this
asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to
21.6.9 Synchronization for further details.
Related Links
16.6.2.6 Peripheral Clock Masking
15. GCLK - Generic Clock Controller
21.5.4 DMA
Not applicable.
SAM D21 Family
EIC – External Interrupt Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 366