Datasheet

20.10.1 Block Transfer Control
Name: BTCTRL
Offset: 0x00
Property: -
The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Bit 15 14 13 12 11 10 9 8
STEPSIZE[2:0] STEPSEL DSTINC SRCINC BEATSIZE[1:0]
Access
Reset
Bit 7 6 5 4 3 2 1 0
BLOCKACT[1:0] EVOSEL[1:0] VALID
Access
Reset
Bits 15:13 – STEPSIZE[2:0] Address Increment Step Size
These bits select the address increment step size. The setting apply to source or destination address,
depending on STEPSEL setting.
Value Name Description
0x0
X1 Next ADDR = ADDR + (Beat size in byte) * 1
0x1
X2 Next ADDR = ADDR + (Beat size in byte) * 2
0x2
X4 Next ADDR = ADDR + (Beat size in byte) * 4
0x3
X8 Next ADDR = ADDR + (Beat size in byte) * 8
0x4
X16 Next ADDR = ADDR + (Beat size in byte) * 16
0x5
X32 Next ADDR = ADDR + (Beat size in byte) * 32
0x6
X64 Next ADDR = ADDR + (Beat size in byte) * 64
0x7
X128 Next ADDR = ADDR + (Beat size in byte) * 128
Bit 12 – STEPSEL Step Selection
This bit selects if source or destination addresses are using the step size settings.
Value Name Description
0x0
DST Step size settings apply to the destination address
0x1
SRC Step size settings apply to the source address
Bit 11 – DSTINC Destination Address Increment Enable
Writing a '0' to this bit will disable the destination address incrementation. The address will be kept fixed
during the data transfer.
Writing a '1' to this bit will enable the destination address incrementation. By default, the destination
address is incremented by 1. If the STEPSEL bit is cleared, flexible step-size settings are available in the
STEPSIZE register.
Value Description
0
The Destination Address Increment is disabled.
1
The Destination Address Increment is enabled.
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 358