Datasheet

20.8.21 Channel Interrupt Enable Set
Name: CHINTENSET
Offset: 0x4D
Reset: 0x00
Property: PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Bit 7 6 5 4 3 2 1 0
SUSP TCMPL TERR
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – SUSP Channel Suspend Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel
Suspend interrupt.
Value Description
0
The Channel Suspend interrupt is disabled.
1
The Channel Suspend interrupt is enabled.
Bit 1 – TCMPL Channel Transfer Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the
Channel Transfer Complete interrupt.
Value Description
0
The Channel Transfer Complete interrupt is disabled.
1
The Channel Transfer Complete interrupt is enabled.
Bit 0 – TERR Channel Transfer Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel
Transfer Error interrupt.
Value Description
0
The Channel Transfer Error interrupt is disabled.
1
The Channel Transfer Error interrupt is enabled.
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 354