Datasheet

ManualsBrandsMicrochip ManualsARM MicrocontrollersARM® Cortex® M0+ SAM Microcontroller 32bit 256KB TQFP

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Value Name Description

0x25

TC7 MC0 TC7 Match/Compare 0 Trigger

0x26

TC7 MC1 TC7 Match/Compare 1 Trigger

0x27

ADC RESRDY ADC Result Ready Trigger

0x28

DAC EMPTY DAC Empty Trigger

0x29

I2S RX 0 I2S RX 0 Trigger

0x2A

I2S RX 1 I2S RX 1 Trigger

0x2B

I2S TX 0 I2S TX 0 Trigger

0x2C

I2S TX 0 I2S TX 1 Trigger

0x2D

OVF TCC3 Overflow Trigger

0x2E

TCC3 MC0 TCC3 Match/Compare 0 Trigger

0x2F

TCC3 MC1 TCC3 Match/Compare 1 Trigger

0x30

TCC3 MC2 Match/Compare 2 Trigger

0x31

TCC3 MC3 Match/Compare 3 Trigger

Bits 6:5 – LVL[1:0] Channel Arbitration Level

These bits define the arbitration level used for the DMA channel, where a high level has priority over a

low level. For further details on arbitration schemes, refer to 20.6.2.4 Arbitration.

These bits are not enable-protected.

TRIGACT[1:0] Name Description

0x0 LVL0 Channel Priority Level 0

0x1 LVL1 Channel Priority Level 1

0x2 LVL2 Channel Priority Level 2

0x3 LVL3 Channel Priority Level 3

Bit 4 – EVOE Channel Event Output Enable

This bit indicates if the Channel event generation is enabled. The event will be generated for every

condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).

This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer

Selection and Event Generator Selection of the Event System for details.

Value Description

Channel event generation is disabled

Channel event generation is enabled

Bit 3 – EVIE Channel Event Input Enable

This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer

Selection and Event Generator Selection of the Event System for details.

Value Description

Channel event action will not be executed on any incoming event

Channel event action will be executed on any incoming event

Bits 2:0 – EVACT[2:0] Event Input Action

These bits define the event input action, as shown below. The action is executed only if the

corresponding EVIE bit in CHCTRLB register of the channel is set.

SAM D21 Family

DMAC – Direct Memory Access Controller

Datasheet Complete

DS40001882D-page 351