Datasheet

20.8.18 Channel Control A

Name: CHCTRLA

Offset: 0x40

Reset: 0x00

Property: PAC Write-Protection, Enable-Protected

This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).

Bit 7 6 5 4 3 2 1 0

ENABLE SWRST

Access

R R R R R R/W R/W

Reset 0 0 0 0 0 0 0

Bit 1 – ENABLE Channel Enable

Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer

buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the

ongoing burst transfer is completed.

Writing a '1' to this bit will enable the DMA channel.

This bit is not enable-protected.

Value Description

DMA channel is disabled.

DMA channel is enabled.

Bit 0 – SWRST Channel Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the

channel is disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is

automatically cleared when the reset is completed.

Value Description

There is no reset operation ongoing.

The reset operation is ongoing.

SAM D21 Family

DMAC – Direct Memory Access Controller

Datasheet Complete

DS40001882D-page 348