Datasheet

20.8.12 Busy Channels
Name: BUSYCH
Offset: 0x28
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
BUSYCHn[11:8]
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BUSYCHn[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 11:0 – BUSYCHn[11:0] Busy Channel n [x=11..0]
This bit is cleared when the channel trigger action for DMA channel n is complete, when a bus error for
DMA channel n is detected, or when DMA channel n is disabled.
This bit is set when DMA channel n starts a DMA transfer.
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 342