Datasheet

20.8.11 Interrupt Status
Name: INTSTATUS
Offset: 0x24
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CHINTn[11:8]
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CHINTn[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 11:0 – CHINTn[11:0] Channel n Pending Interrupt [n=11..0]
This bit is set when Channel n has a pending interrupt/the interrupt request is received.
This bit is cleared when the corresponding Channel n interrupts are disabled or the interrupts sources are
cleared.
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 341