Datasheet

20.8.2 CRC Control
Name: CRCCTRL
Offset: 0x02
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected
Bit 15 14 13 12 11 10 9 8
CRCSRC[5:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CRCPOLY[1:0] CRCBEATSIZE[1:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 13:8 – CRCSRC[5:0] CRC Input Source
These bits select the input source for generating the CRC, as shown in the table below. The selected
source is locked until either the CRC generation is completed or the CRC module is disabled. This means
the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the
CRCBUSY Status bit. CRC generation complete is generated and signaled from the selected source
when used with the DMA channel.
Value Name Description
0x00
NOACT No action
0x01
IO I/O interface
0x02-0x
1F
- Reserved
0x20
CHN DMA channel 0
0x21
CHN DMA channel 1
0x22
CHN DMA channel 2
0x23
CHN DMA channel 3
0x24
CHN DMA channel 4
0x25
CHN DMA channel 5
0x26
CHN DMA channel 6
0x27
CHN DMA channel 7
0x28
CHN DMA channel 8
0x29
CHN DMA channel 9
0x2A
CHN DMA channel 10
0x2B
CHN DMA channel 11
Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type
These bits define the size of the data transfer for each bus access when the CRC is used with I/O
interface, as shown in the table below.
Value Name Description
0x0
CRC16 CRC-16 (CRC-CCITT)
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 329