Datasheet

...........continued
Offset Name Bit Pos.
0x2C PENDCH
7:0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0
15:8 PENDCH11 PENDCH10 PENDCH9 PENDCH8
23:16
31:24
0x30 ACTIVE
7:0 LVLEXx LVLEXx LVLEXx LVLEXx
15:8 ABUSY ID[4:0]
23:16 BTCNT[7:0]
31:24 BTCNT[15:8]
0x34 BASEADDR
7:0
15:8
23:16
31:24
0x38 WRBADDR
7:0
15:8
23:16
31:24
0x3C
...
0x3E
Reserved
0x3F CHID 7:0 ID[3:0]
0x40 CHCTRLA 7:0 ENABLE SWRST
0x41
...
0x43
Reserved
0x44 CHCTRLB
7:0 LVL[1:0] EVOE EVIE EVACT[2:0]
15:8 TRIGSRC[5:0]
23:16 TRIGACT[1:0]
31:24 CMD[1:0]
0x48
...
0x4B
Reserved
0x4C CHINTENCLR 7:0 SUSP TCMPL TERR
0x4D CHINTENSET 7:0 SUSP TCMPL TERR
0x4E CHINTFLAG 7:0 SUSP TCMPL TERR
0x4F CHSTATUS 7:0 FERR BUSY PEND
20.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC
write-protection is denoted by the "PAC Write-Protection" property in each individual register description.
For details, refer to 20.5.8 Register Access Protection.
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 325