Datasheet

Figure 20-9. Destination Address Increment

DST Data Buffer

20.6.2.8 Error Handling

If a bus error is received from an AHB slave during a DMA data transfer, the corresponding active

channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt

Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is

generated. The transfer counter will not be decremented and its current value is written-back in the write-

back memory section before the channel is disabled.

When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and

the DMA fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding

channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status

and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status

20.6.3 Additional Features

20.6.3.1 Linked Descriptors

A transaction can consist of either a single block transfer or of several block transfers. When a

transaction consists of several block transfers it is done with the help of linked descriptors.

Figure 20-3 illustrates how linked descriptors work. When the first block transfer is completed on DMA

channel 0, the DMAC fetches the next transfer descriptor, which is pointed to by the value stored in the

Next Descriptor Address (DESCADDR) register of the first transfer descriptor. Fetching the next transfer

descriptor (DESCADDR) is continued until the last transfer descriptor. When the block transfer for the last

transfer descriptor is executed and DESCADDR=0x00000000, the transaction is terminated. For further

details on how the next descriptor is fetched from SRAM, refer to section 20.6.2.5 Data Transmission.

20.6.3.1.1 Adding Descriptor to the End of a List

To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with

DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the

DESCADDR value of the current last descriptor to the address of the newly created descriptor.

20.6.3.1.2 Modifying a Descriptor in a List

In order to add descriptors to a linked list, the following actions must be performed:

1. Enable the Suspend interrupt for the DMA channel.

2. Enable the DMA channel.

3. Reserve memory space in SRAM to configure a new descriptor.

4. Configure the new descriptor:

SAM D21 Family

DMAC – Direct Memory Access Controller

Datasheet Complete

DS40001882D-page 314