Datasheet

Figure 20-8. Source Address Increment

SRC Data Buffer

Incrementation for the destination address of a block transfer is enabled by setting the Destination

Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step

size of the incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing

BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL=1, the step size for the destination

incrementation will be the size of one beat.

When the destination address incrementation is configured (BTCTRL.DSTINC=1), DSTADDR must be

set and calculated as follows:

 = 



+  •  + 1 • 2



where BTCTRL.STEPSEL is zero

 = 



+  •  + 1 where BTCTRL.STEPSEL is one

• DSTADDR

START

is the destination address of the first beat transfer in the block transfer

• BTCNT is the initial number of beats remaining in the block transfer

• BEATSIZE is the configured number of bytes in a beat

• STEPSIZE is the configured number of beats for each incrementation

The followiong figure shows an example where DMA channel 0 is configured to increment destination

address by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination

address by two beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As

the source address for both channels are peripherals, source incrementation is disabled

(BTCTRL.SRCINC=0).

SAM D21 Family

DMAC – Direct Memory Access Controller

Datasheet Complete

DS40001882D-page 313