Datasheet

20.6.2.4 Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer
request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the
queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending
Channels registers (PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter
will choose which DMA channel will be the next active channel. The active channel is the DMA channel
being granted access to perform its next burst transfer. When the arbiter has granted a DMA channel
access to the DMAC, the corresponding bit PENDCH.PENDCHx will be cleared. See also the following
figure.
If the upcoming burst transfer is the first for the transfer request, the corresponding Busy Channel x bit in
the Busy Channels register will be set (BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent
granted burst transfers.
When the channel has performed its granted burst transfer(s) it will be either fed into the queue of
channels with pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This
depends on the channel and block transfer configuration. If the DMA channel is fed into the queue of
channels with pending transfers, the corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA
channel is set to wait for a new transfer trigger, suspended, or disabled, the corresponding
BUSYCH.BUSYCHx will be cleared.
If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of
pending channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA
channel is resumed, it will be added to the queue of pending channels again.
If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed
from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared.
Figure 20-4. Arbiter Overview
Channel 0
Channel N
Active
Channel
Priority
decoder
Active.LVLEXx
PRICTRLx.LVLPRI
Arbiter
CTRL.LVLENx
Burst Done
Transfer Request
Channel Number
Level Enable
Channel Burst Done
Channel Priority Level
Channel Pending
Channel Suspend
Channel Burst Done
Channel Priority Level
Channel Pending
Channel Suspend
Priority Levels
When a channel level is pending or the channel is transferring data, the corresponding Level Executing
bit is set in the Active Channel and Levels register (ACTIVE.LVLEXx).
Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by
writing to the Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As
long as all priority levels are enabled, a channel with a higher priority level number will have priority over
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 308