Datasheet

20.6.2 Basic Operation
20.6.2.1 Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the
DMAC is disabled (CTRL.DMAENABLE=0):
• Descriptor Base Memory Address register (BASEADDR)
• Write-Back Memory Base Address register (WRBADDR)
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and
CRC are disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0):
• Software Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the
corresponding DMA channel is disabled (CHCTRLA.ENABLE=0):
• Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the
Channel Arbitration Level bit (CHCTRLB.LVL)
The following DMA channel bit is enable-protected, meaning that it can only be written when the
corresponding DMA channel is disabled:
• Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC
is disabled (CTRL.CRCENABLE=0):
• CRC Control register (CRCCTRL)
• CRC Checksum register (CRCCHKSUM)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
Before the DMAC is enabled it must be configured, as outlined by the following steps:
• The SRAM address of where the descriptor memory section is located must be written to the
Description Base Address (BASEADDR) register
• The SRAM address of where the write-back section should be located must be written to the Write-
Back Memory Base Address (WRBADDR) register
• Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control
register (CTRL.LVLENx=1)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must
be configured, as outlined by the following steps:
• DMA channel configurations
– The channel number of the DMA channel to configure must be written to the Channel ID
(CHID) register
– Trigger action must be selected by writing the Trigger Action bit group in the Channel Control
B register (CHCTRLB.TRIGACT)
– Trigger source must be selected by writing the Trigger Source bit group in the Channel
Control B register (CHCTRLB.TRIGSRC)
• Transfer Descriptor
– The size of each access of the data transfer bus must be selected by writing the Beat Size bit
group in the Block Transfer Control register (BTCTRL.BEATSIZE)
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 305