Datasheet

An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock must be configured and
enabled in the power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be
found in Peripheral Clock Masking.
This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but
can be divided by a prescaler and may run even when the module clock is turned off.
Related Links
16.6.2.6 Peripheral Clock Masking
20.5.4 DMA
Not applicable.
20.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the
interrupt controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
20.5.6 Events
The events are connected to the event system.
Related Links
24. EVSYS – Event System
20.5.7 Debug Operation
When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced
to continue operation during debugging. Refer to 20.8.6 DBGCTRL for details.
20.5.8 Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller
(PAC), except for the following registers:
• Interrupt Pending register (INTPEND)
• Channel ID register (CHID)
• Channel Interrupt Flag Status and Clear register (CHINTFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
11.6 PAC - Peripheral Access Controller
20.5.9 Analog Connections
Not applicable.
20.6 Functional Description
20.6.1 Principle of Operation
The DMAC consists of a DMA module and a CRC module.
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 303