Datasheet

20.3 Block Diagram
Figure 20-1. DMAC Block Diagram
HIGH SPEED
BUS MATRIX
AHB/APB
Bridge
CPU
SRAM
S
S
M
M
Events
Channel 0
Channel 1
Channel n
Arbiter
DMA Channels
MASTER
Active
Channel
CRC
Engine
n
Fetch
Engine
Interrupt /
Events
DMAC
Interrupts
Transfer
Triggers
n
Data Transfer
Write-back
Descriptor Fetch
20.4 Signal Description
Not applicable.
20.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
20.5.1 I/O Lines
Not applicable.
20.5.2 Power Management
The DMAC will continue to operate in any sleep mode where the selected source clock is running. The
DMAC’s interrupts can be used to wake up the device from sleep modes. Events connected to the event
system can trigger other operations in the system without exiting sleep modes. On hardware or software
reset, all registers are set to their reset value.
Related Links
16. PM – Power Manager
20.5.3 Clocks
The DMAC bus clock (CLK_DMAC_APB) must be configured and enabled in the Power Manager before
using the DMAC.
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 302