Datasheet

20. DMAC – Direct Memory Access Controller
20.1 Overview
The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access (DMA) engine and
a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and
peripherals and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum
CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle
automatic transfer of data between communication modules.
The DMA part of the DMAC has several DMA channels, which can receive different types of transfer
triggers to generate transfer requests from the DMA channels to the arbiter, as shown in the Block
Diagram. The arbiter will grant one DMA channel at a time to act as the active channel. When an active
channel has been granted, the fetch engine of the DMAC will fetch a transfer descriptor from the SRAM
and store it in the internal memory of the active channel, which will execute the data transmission.
An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel.
The DMAC will write back the updated transfer descriptor from the internal memory of the active channel
to SRAM, and grant the higher prioritized channel a start transfer as the new active channel. Once a DMA
channel is done with its transfer, interrupts and events can be generated optionally.
The DMAC has four bus interfaces:
• The data transfer bus is used for performing the actual DMA transfer.
• The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC.
• The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data
transfer can be started or continued.
• The write-back bus is used to write the transfer descriptor back to SRAM.
All buses are AHB master interfaces but the AHB/APB Bridge bus, which is an APB slave interface.
The CRC engine can be used by software to detect an accidental error in the transferred data and to take
corrective action, such as requesting the data to be sent again or simply not using the incorrect data.
20.2 Features
• Data Transfer From:
– Peripheral-to-peripheral
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
• Transfer Trigger Sources:
– Software
– Events from Event System
– Dedicated requests from peripherals
• SRAM-based Transfer Descriptors:
– Single transfer using one descriptor
– Multi-buffer or Circular Buffer modes by linking multiple descriptors
SAM D21 Family
DMAC – Direct Memory Access Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
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