Datasheet

19.8.16 Interrupt Flag Status and Clear - MODE2

Name: INTFLAG

Offset: 0x08

Reset: 0x00

Property: -

Bit 7 6 5 4 3 2 1 0

OVF SYNCRDY ALARM0

Access

R/W R/W R/W

Reset 0 0 0

Bit 7 – OVF Overflow

This flag is cleared by writing a one to the flag.

This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt

request will be generated if INTENCLR/SET.OVF is one.

Writing a zero to this bit has no effect.

Writing a one to this bit clears the Overflow interrupt flag.

Bit 6 – SYNCRDY Synchronization Ready

This flag is cleared by writing a one to the flag.

This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register

(STATUS.SYNCBUSY), except when caused by enable or software reset, and an interrupt request will be

generated if INTENCLR/SET.SYNCRDY is one.

Writing a zero to this bit has no effect.

Writing a one to this bit clears the Synchronization Ready interrupt flag.

Bit 0 – ALARM0 Alarm 0

This flag is cleared by writing a one to the flag.

This flag is set on the next CLK_RTC_CNT cycle after a match with ALARM0 condition occurs, and an

interrupt request will be generated if INTENCLR/SET.ALARM0 is also one.

Writing a zero to this bit has no effect.

Writing a one to this bit clears the Alarm 0 interrupt flag.

SAM D21 Family

RTC – Real-Time Counter

Datasheet Complete

DS40001882D-page 287