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19.8.11 Interrupt Enable Set - MODE0
Name:  INTENSET
Offset:  0x07
Reset:  0x00
Property:  Write-Protected
Bit 7 6 5 4 3 2 1 0
OVF SYNCRDY CMP0
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 – OVF Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
Value Description
0
The overflow interrupt is disabled.
1
The overflow interrupt is enabled.
Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the
Synchronization Ready interrupt.
Value Description
0
The synchronization ready interrupt is disabled.
1
The synchronization ready interrupt is enabled.
Bit 0 – CMP0 Compare 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt.
Value Description
0
The compare 0 interrupt is disabled.
1
The compare 0 interrupt is enabled.
SAM D21 Family
RTC – Real-Time Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 282