Datasheet
7. I/O Multiplexing and Considerations
7.1 Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a
pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function
A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing
register (PMUXn.PMUXE/O) in the PORT.
This table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 7-1. PORT Function Multiplexing for A, B, C and D Variant Devices
Pin
(1)
I/O Pin Supply A B
(2)(3)
C D E F G H
SAMD21E SAMD21G SAMD21J EIC REF ADC AC PTC DAC SERCOM
(2)(3)
SERCOM-ALT TC
(4)
/TCC
TCC COM AC/
GCLK
1 1 1 PA00 VDDANA EXTINT[0] SERCOM1/
PAD[0]
TCC2/WO[0]
2 2 2 PA01 VDDANA EXTINT[1] SERCOM1/
PAD[1]
TCC2/WO[1]
3 3 3 PA02 VDDANA EXTINT[2] AIN[0] Y[0] VOUT TCC3/
WO[0]
4 4 4 PA03 VDDANA EXTINT[3] ADC/
VREFA
DAC/
VREFA
AIN[1] Y[1] TCC3/
WO[1]
5 PB04 VDDANA EXTINT[4] AIN[12] Y[10]
6 PB05 VDDANA EXTINT[5] AIN[13] Y[11]
9 PB06 VDDANA EXTINT[6] AIN[14] Y[12]
10 PB07 VDDANA EXTINT[7] AIN[15] Y[13]
7 11 PB08 VDDANA EXTINT[8] AIN[2] Y[14] SERCOM4/
PAD[0]
TC4/WO[0] TCC3/
WO[6]
8 12 PB09 VDDANA EXTINT[9] AIN[3] Y[15] SERCOM4/
PAD[1]
TC4/WO[1] TCC3/
WO[7]
5 9 13 PA04 VDDANA EXTINT[4] ADC/
VREFB
AIN[4] AIN[0] Y[2] SERCOM0/
PAD[0]
TCC0/WO[0] TCC3/
WO[2]
6 10 14 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/
PAD[1]
TCC0/WO[1] TCC3/
WO[3]
7 11 15 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/
PAD[2]
TCC1/WO[0] TCC3/
WO[4]
8 12 16 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/
PAD[3]
TCC1/WO[1] TCC3/
WO[5]
I2S/SD[0]
11 13 17 PA08 VDDIO NMI AIN[16] X[0] SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/WO[0] TCC1/
WO[2]
I2S/SD[1]
12 14 18 PA09 VDDIO EXTINT[9] AIN[17] X[1] SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC0/WO[1] TCC1/
WO[3]
I2S/
MCK[0]
13 15 19 PA10 VDDIO EXTINT[10] AIN[18] X[2] SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC1/WO[0] TCC0/
WO[2]
I2S/
SCK[0]
GCLK_IO[4]
14 16 20 PA11 VDDIO EXTINT[11] AIN[19] X[3] SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC1/WO[1] TCC0/
WO[3]
I2S/FS[0] GCLK_IO[5]
19 23 PB10 VDDIO EXTINT[10] SERCOM4/
PAD[2]
TC5/WO[0] TCC0/
WO[4]
I2S/
MCK[1]
GCLK_IO[4]
20 24 PB11 VDDIO EXTINT[11] SERCOM4/
PAD[3]
TC5/WO[1] TCC0/
WO[5]
I2S/
SCK[1]
GCLK_IO[5]
25 PB12 VDDIO EXTINT[12] X[12] SERCOM4/
PAD[0]
TC4/WO[0] TCC0/
WO[6]
I2S/FS[1] GCLK_IO[6]
SAM D21 Family
I/O Multiplexing and Considerations
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 28