Datasheet

19.8.8 Interrupt Enable Clear - MODE0
Name: INTENCLR
Offset: 0x06
Reset: 0x00
Property: Write-Protected
Bit 7 6 5 4 3 2 1 0
OVF SYNCRDY CMP0
Access
R/W R/W R/W
Reset 0 0 0
Bit 7 – OVF Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding
interrupt.
Value Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled, and an interrupt request will be generated when the
Overflow interrupt flag is set.
Bit 6 – SYNCRDY Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the
corresponding interrupt.
Value Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled, and an interrupt request will be generated
when the Synchronization Ready interrupt flag is set.
Bit 0 – CMP0 Compare 0 Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare 0 Interrupt Enable bit and disable the corresponding
interrupt.
Value Description
0
The Compare 0 interrupt is disabled.
1
The Compare 0 interrupt is enabled, and an interrupt request will be generated when the
Compare x interrupt flag is set.
SAM D21 Family
RTC – Real-Time Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 279