Datasheet

19.8.4 Read Request
Name: READREQ
Offset: 0x02
Reset: 0x0010
Property: -
Bit 15 14 13 12 11 10 9 8
RREQ RCONT
Access
W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[5:0]
Access
R R R R R R
Reset 0 1 0 0 0 0
Bit 15 – RREQ Read Request
Writing a zero to this bit has no effect.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group
(READREQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
Bit 14 – RCONT Read Continuously
Writing a zero to this bit disables continuous synchronization.
Writing a one to this bit enables continuous synchronization of the register pointed to by
READREQ.ADDR. The register value will be synchronized automatically every time the register is
updated. READREQ.RCONT prevents READREQ.RREQ from clearing automatically. For the continuous
read mode, RREQ bit is required to be set once the RCONT bit is set.
This bit is cleared when an RTC register is written.
Bits 5:0 – ADDR[5:0] Address
These bits select the offset of the register that needs read synchronization. In the RTC only COUNT and
CLOCK, which share the same address, are available for read synchronization. Therefore, ADDR is a
read-only constant of 0x10.
SAM D21 Family
RTC – Real-Time Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 275