Datasheet

19.8.3 Control - MODE2
Name: CTRL
Offset: 0x00
Reset: 0x0000
Property: Enable-Protected, Write-Protected, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
PRESCALER[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MATCHCLR CLKREP MODE[1:0] ENABLE SWRST
Access
R/W R/W R/W R/W R/W W
Reset 0 0 0 0 0 0
Bits 11:8 – PRESCALER[3:0] Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter
clock (CLK_RTC_CNT).
These bits are not synchronized.
PRESCALER[3:0] Name Description
0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1
0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2
0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4
0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8
0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16
0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32
0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64
0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128
0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256
0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512
0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF Reserved
Bit 7 – MATCHCLR Clear on Match
This bit is valid only in Mode 0 and Mode 2. This bit can be written only when the peripheral is disabled.
This bit is not synchronized.
Value Description
0
The counter is not cleared on a Compare/Alarm 0 match.
SAM D21 Family
RTC – Real-Time Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 272