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19.6.7 Sleep Mode Operation

The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts

can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the

system without exiting the sleep mode.

An interrupt request will be generated after the wake-up if the Interrupt Controller is configured

accordingly. Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the

CPU will continue executing right from the first instruction that followed the entry into sleep.

The periodic events can also wake up the CPU through the interrupt function of the Event System. In this

case, the event must be enabled and connected to an event channel with its interrupt enabled. See Event

System for more information.

Related Links

24. EVSYS – Event System

19.6.8 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

When executing an operation that requires synchronization, the Synchronization Busy bit in the Status

The Synchronization Ready interrupt can be used to signal when synchronization is complete. This can

be accessed via the Synchronization Ready Interrupt Flag in the Interrupt Flag Status and Clear register

(INTFLAG.SYNCRDY). If an operation that requires synchronization is executed while

STATUS.SYNCBUSY is one, the bus will be stalled. All operations will complete successfully, but the

CPU will be stalled and interrupts will be pending as long as the bus is stalled.

The following bits are synchronized when written:

• Software Reset bit in the Control register (CTRL.SWRST)

• Enable bit in the Control register (CTRL.ENABLE)

The following registers are synchronized when written:

• Counter Value register (COUNT)

• Clock Value register (CLOCK)

• Counter Period register (PER)

• Compare n Value registers (COMPn)

• Alarm n Value registers (ALARMn)

• Frequency Correction register (FREQCORR)

• Alarm n Mask register (MASKn)

Required write-synchronization is denoted by the "Write-Synchronized" property in the register

description.

The following registers are synchronized when read:

• The Counter Value register (COUNT)

• The Clock Value register (CLOCK)

Required read-synchronization is denoted by the "Read-Synchronized" property in the register

description.