Datasheet

Periodic Events). Note that when CTRL.MATCHCLR is '1', INTFLAG.ALARM0 and INTFLAG.OVF will

both be set simultaneously on an alarm match with ALARM0.

19.6.4 DMA Operation

Not applicable.

19.6.5 Interrupts

The RTC has the following interrupt sources which are asynchronous interrupts and can wake-up the

device from any sleep mode.:

• Overflow (INTFLAG.OVF): Indicates that the counter has reached its top value and wrapped to

zero.

• Compare n (INTFLAG.CMPn): Indicates a match between the counter value and the compare

• Alarm n (INTFLAG.ALARMn): Indicates a match between the clock value and the alarm register.

• Synchronization Ready (INTFLAG.SYNCRDY): Indicates an operation requires synchronization.

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status

and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be

individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1),

and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). An

interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is enabled.

The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled or the

RTC is reset. See the description of the INTFLAG registers for details on how to clear interrupt flags. All

interrupt requests from the peripheral are ORed together on system level to generate one combined

interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must

read the INTFLAG register to determine which interrupt condition is present.

Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested

Vector Interrupt Controller for details.