Datasheet

Enable-protection is denoted by the "Enable-Protected" property in the register description.
Before the RTC is enabled, it must be configured, as outlined by the following steps:
1. RTC operation mode must be selected by writing the Operating Mode bit group in the Control
register (CTRL.MODE)
2. Clock representation must be selected by writing the Clock Representation bit in the Control
register (CTRL.CLKREP)
3. Prescaler value must be selected by writing the Prescaler bit group in the Control register
(CTRL.PRESCALER)
The RTC prescaler divides the source clock for the RTC counter.
Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter
for correct operation.
The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula:

CLK_RTC_CNT
=

GCLK_RTC
2
PRESCALER
The frequency of the generic clock, GCLK_RTC, is given by f
GCLK_RTC
, and f
CLK_RTC_CNT
is the frequency
of the internal prescaled RTC clock, CLK_RTC_CNT.
19.6.2.2 Enabling, Disabling and Resetting
The RTC is enabled by setting the Enable bit in the Control register (CTRL.ENABLE=1). The RTC is
disabled by writing CTRL.ENABLE=0.
The RTC is reset by setting the Software Reset bit in the Control register (CTRL.SWRST=1). All registers
in the RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The RTC must
be disabled before resetting it.
19.6.3 Operating Modes
The RTC counter supports three RTC operating modes: 32-bit Counter, 16-bit Counter and Clock/
Calendar. The operating mode is selected by writing to the Operating Mode bit group in the Control
register (CTRL.MODE).
19.6.3.1 32-Bit Counter (Mode 0)
When the RTC Operating Mode bits in the Control register are zero (CTRL.MODE=00), the counter
operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 19-1. When the RTC
is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will
increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the
Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit
format.
The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare
match occurs, the Compare 0interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.CMP0) is set on the next 0-to-1 transition of CLK_RTC_CNT.
If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is '1', the counter is cleared on the
next counter cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic
interrupts or events with longer periods than are possible with the prescaler events. Note that when
CTRL.MATCHCLR is '1', INTFLAG.CMP0 and INTFLAG.OVF will both be set simultaneously on a
compare match with COMP0.
SAM D21 Family
RTC – Real-Time Counter
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 260