Datasheet

18.8.7 Status
Name: STATUS
Offset: 0x7
Reset: 0x00
Property: –
Bit 7 6 5 4 3 2 1 0
SYNCBUSY
Access
R
Reset 0
Bit 7 – SYNCBUSY Synchronization Busy
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
SAM D21 Family
WDT – Watchdog Timer
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 254