Datasheet

18.7 Register Summary

Offset Name Bit Pos.

0x00 CTRL 7:0 ALWAYSON WEN ENABLE

0x01 CONFIG 7:0 WINDOW[3:0] PER[3:0]

0x02 EWCTRL 7:0 EWOFFSET[3:0]

0x03 Reserved

0x04 INTENCLR 7:0 EW

0x05 INTENSET 7:0 EW

0x06 INTFLAG 7:0 EW

0x07 STATUS 7:0 SYNCBUSY

0x08 CLEAR 7:0 CLEAR[7:0]

18.8 Register Description

Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,

the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be

accessed directly.

Some registers require synchronization when read and/or written. Synchronization is denoted by the

"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.

Some registers are enable-protected, meaning they can only be written when the module is disabled.

Enable-protection is denoted by the "Enable-Protected" property in each individual register description.

Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-

Protection" property in each individual register description.

SAM D21 Family

WDT – Watchdog Timer

Datasheet Complete

DS40001882D-page 245