Datasheet

period, the watchdog time-out system reset is generated prior to the Early Warning interrupt. Thus, the

Early Warning interrupt will never be generated.

In window mode, the Early Warning interrupt is generated at the start of the open window period. In a

typical application where the system is in sleep mode, it can use this interrupt to wake up and clear the

Watchdog Timer, after which the system can perform other tasks or return to sleep mode.

18.6.5 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

When executing an operation that requires synchronization, the Synchronization Busy bit in the Status

If an operation that requires synchronization is executed while STATUS.SYNCBUSY='1', the bus will be

stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending

as long as the bus is stalled.

The following registers are synchronized when written:

• Control register (CTRL)

• Clear register (CLEAR)

Required write-synchronization is denoted by the "Write-Synchronized" property in the register

description.