Datasheet

(INTENCLR.EW). If the Early Warning Interrupt is enabled, an interrupt is generated prior to a WDT time-
out condition. In Normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control
register, EWCTRL.EWOFFSET, define the time when the early warning interrupt occurs. The Normal
mode operation is illustrated in the figure Normal-Mode Operation.
Figure 18-2. Normal-Mode Operation
5 10 15 20 25 30 35
WDT Timeout
Early Warning Interrupt
Timely WDT Clear
t[ms]
TO
WDT
System Reset
WDT Count
PER[3:0] = 1
EWOFFSET[3:0] = 0
18.6.2.5 Window Mode
In Window mode operation, the WDT uses two different time specifications: the WDT can only be cleared
by writing 0xA5 to the CLEAR register after the closed window time-out period (TO
WDTW
), during the
subsequent Normal time-out period (TO
WDTW
). If the WDT is cleared before the time window opens
(before TO
WDTW
is over), the WDT will issue a system reset. Both parameters TO
WDTW
and TO
WDT
are
periods in a range from 8ms to 16s, so the total duration of the WDT time-out period is the sum of the two
parameters. The closed window period is defined by the Window Period bits in the Configuration register
(CONFIG.WINDOW), and the open window period is defined by the Period bits in the Configuration
register (CONFIG.PER).
By default, the Early Warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in
the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is
disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear
(INTENCLR.EW) register. If the Early Warning interrupt is enabled in Window mode, the interrupt is
generated at the start of the open window period, i.e. after TO
WDTW
. The Window mode operation is
illustrated in figure Window-Mode Operation.
Figure 18-3. Window-Mode Operation
5 10 15 20 25 30 35
WDT Timeout
Early Warning Interrupt
Timely WDT Clear
t[ms]
TO
WDT
System Reset
WDT Count
PER[3:0] = 0
WINDOW[3:0] = 0
TO
WDTW
Early WDT Clear
Closed Open
18.6.3 Additional Features
18.6.3.1 Always-On Mode
The Always-On mode is enabled by setting the Always-On bit in the Control register
(CTRLA.ALWAYSON=1). When the Always-On mode is enabled, the WDT runs continuously, regardless
of the state of CTRL.ENABLE. Once written, the Always-On bit can only be cleared by a power-on reset.
SAM D21 Family
WDT – Watchdog Timer
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 242