Datasheet

Window Mode
• Defining Time-Out Period bits in the Configuration register (CONFIG.PER).
• Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
• Setting Window Enable bit in the Control register (CTRL.WEN).
Window Mode with Early Warning interrupt
• Defining Time-Out Period bits in the Configuration register (CONFIG.PER).
• Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
• Setting Window Enable bit in the Control register (CTRL.WEN).
• Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register
(EWCTRL. EWOFFSET).
• Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).
18.6.2.2 Configurable Reset Values
After a Power-on Reset, some registers will be loaded with initial values from the NVM User Row. Refer
to NVM User Row Mapping for more details.
This encompasses the following bits and bit groups:
• Enable bit in the Control register, CTRL.ENABLE
• Always-On bit in the Control register, CTRL.ALWAYSON
• Watchdog Timer Windows Mode Enable bit in the Control register, CTRL.WEN
• Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register,
CONFIG.WINDOW
• Time-Out Period in the Configuration register, CONFIG.PER
• Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register,
EWCTRL.EWOFFSET
For more information about fuse locations, see NVM User Row Mapping.
Related Links
10.3.1 NVM User Row Mapping
18.6.2.3 Enabling and Disabling
The WDT is enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). The WDT is
disabled by writing a '0' to CTRL.ENABLE.
The WDT can be disabled only if the Always-On bit in the Control register (CTRL.ALWAYSON) is '0'.
18.6.2.4 Normal Mode
In Normal mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is
enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). Once enabled, the WDT
will issue a system reset if a time-out occurs. This can be prevented by clearing the WDT at any time
during the time-out period.
The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register
(CLEAR). Writing any other value than 0xA5 to CLEAR will issue an immediate system reset.
There are 12 possible WDT time-out (TO
WDT
) periods, selectable from 8ms to 16s.
By default, the early warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in
the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is
disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear register
SAM D21 Family
WDT – Watchdog Timer
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 241