Datasheet

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constantly running timer that is configured to a predefined time-out period. Before the end of the time-out

period, the WDT should be set back, or else, a system Reset is issued.

The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of

Early Warning interrupt generation. The description for each of the basic modes is given below. The

settings in the Control register (CTRL) and the Interrupt Enable register (handled by INTENCLR/SET)

determine the mode of operation:

Table 18-1. WDT Operating Modes

CTRL.ENABLE CTRL.WEN INTENSET.EW Mode

0 x x Stopped

1 0 0 Normal

1 0 1 Normal with Early Warning interrupt

1 1 0 Window

1 1 1 Window with Early Warning interrupt

18.6.2 Basic Operation

18.6.2.1 Initialization

The following bits are enable-protected:

• Window Mode Enable in the Control register (CTRL.WEN)

• Always-On in the Control register (CTRL-ALWAYSON)

The following registers are enable-protected:

• Configuration register (CONFIG)

• Early Warning Interrupt Control register (EWCTRL)

Any writes to these bits or registers when the WDT is enabled or is being enabled (CTRL.ENABLE=1) will

be discarded. Writes to these registers while the WDT is being disabled will be completed after the

disabling is complete.

Enable-protection is denoted by the Enable-Protected property in the register description.

Initialization of the WDT can be done only while the WDT is disabled. The WDT is configured by defining

the required Time-Out Period bits in the Configuration register (CONFIG.PER). If window-mode operation

is required, the Window Enable bit in the Control register (CTRL.WEN) must be written to one and the

Window Period bits in the Configuration register (CONFIG.WINDOW) must be defined.

Normal Mode

• Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER).

Normal Mode with Early Warning interrupt

• Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER).

• Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register

(EWCTRL. EWOFFSET).

• Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).

SAM D21 Family

WDT – Watchdog Timer

Datasheet Complete

DS40001882D-page 240