Datasheet

vary from device to device. This variation must be kept in mind when designing software that uses the
WDT to ensure that the time-out periods used are valid for all devices. For more information on ULP
oscillator accuracy, consult the Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K)
Characteristics.
GCLK_WDT can also be clocked from other sources if a more accurate clock is needed, but at the cost of
higher power consumption.
Related Links
16. PM – Power Manager
15. GCLK - Generic Clock Controller
17.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
18.6.5 Synchronization
18.5.4 DMA
Not applicable.
18.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the WDT interrupt(s) requires the
interrupt controller to be configured first.
Related Links
11.2 Nested Vector Interrupt Controller
18.5.6 Events
Not applicable.
18.5.7 Debug Operation
When the CPU is halted in debug mode the WDT will halt normal operation.
18.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• Interrupt Flag Status and Clear register (INTFLAG)
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
Related Links
11.6 PAC - Peripheral Access Controller
18.5.9 Analog Connections
Not applicable.
18.6 Functional Description
18.6.1 Principle of Operation
The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to
recover from error situations such as runaway code, by issuing a Reset. When enabled, the WDT is a
SAM D21 Family
WDT – Watchdog Timer
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 239