Datasheet

18.3 Block Diagram
Figure 18-1. WDT Block Diagram
GCLK_WDT
COUNT
Reset
PER/WINDOW/EWOFFSET
0
CLEAR
0xA5
Early Warning Interrupt
18.4 Signal Description
Not applicable.
18.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
18.5.1 I/O Lines
Not applicable.
18.5.2 Power Management
The WDT can continue to operate in any sleep mode where the selected source clock is running. The
WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other
operations in the system without exiting sleep modes.
Related Links
16. PM – Power Manager
18.5.3 Clocks
The WDT bus clock (CLK_WDT_APB) is enabled by default, and can be enabled and disabled in the
Power Manager. Refer to PM – Power Manager for details.
A generic clock (GCLK_WDT) is required to clock the WDT. This clock must be configured and enabled in
the Generic Clock Controller before using the WDT. Refer to GCLK – Generic Clock Controller for details.
This generic clock is asynchronous to the user interface clock (CLK_WDT_APB). Due to this
asynchronicity, accessing certain registers will require synchronization between the clock domains. Refer
to Synchronization for further details.
GCLK_WDT is intended to be sourced from the clock of the internal ultra-low-power (ULP) oscillator. Due
to the ultralow- power design, the oscillator is not very accurate, and so the exact time-out period may
SAM D21 Family
WDT – Watchdog Timer
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 238