Datasheet

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LTIME[2:0] Name Description
0x7 11MS Time-out if no lock within 11 ms
Bits 5:4 – REFCLK[1:0] Reference Clock Selection
These bits select the CLK_FDPLL96M_REF source.
REFCLK[1:0] Name Description
0x0 XOSC32 XOSC32 clock reference
0x1 XOSC XOSC clock reference
0x2 GCLK_DPLL GCLK_DPLL clock reference
0x3 Reserved
Bit 3 – WUF Wake Up Fast
Value Description
0
DPLL CK output is gated until complete startup time and lock time.
1
DPLL CK output is gated until startup time only.
Bit 2 – LPEN Low-Power Enable
Value Description
0
The time to digital converter is selected.
1
The time to digital converter is not selected, this will improve power consumption but
increase the output jitter.
Bits 1:0 – FILTER[1:0] Proportional Integral Filter Selection
These bits select the DPLL filter type.
FILTER[1:0] Name Description
0x0 DEFAULT Default filter mode
0x1 LBFILT Low bandwidth filter
0x2 HBFILT High bandwidth filter
0x3 HDFILT High damping filter
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 235