Datasheet

17.8.19 DPLL Control B
Name: DPLLCTRLB
Offset: 0x4C
Reset: 0x00000000
Property: Write-Protected
Bit 31 30 29 28 27 26 25 24
DIV[10:8]
Access
R/W R/W R/W
Reset 0 0 0
Bit 23 22 21 20 19 18 17 16
DIV[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
LBYPASS LTIME[2:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
REFCLK[1:0] WUF LPEN FILTER[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 26:16 – DIV[10:0] Clock Divider
These bits are used to set the XOSC clock source division factor. Refer to 17.6.8.3 Principle of
Operation.
Bit 12 – LBYPASS Lock Bypass
Value Description
0
Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1
Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
Bits 10:8 – LTIME[2:0] Lock Time
These bits select Lock Timeout.
LTIME[2:0] Name Description
0x0 DEFAULT No time-out
0x1-0x3 Reserved
0x4 8MS Time-out if no lock within 8 ms
0x5 9MS Time-out if no lock within 9 ms
0x6 10MS Time-out if no lock within 10 ms
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 234