Datasheet

17.8.10 DFLL48M Control
Name: DFLLCTRL
Offset: 0x24
Reset: 0x0080
Property: Write-Protected, Write-Synchronized
Bit 15 14 13 12 11 10 9 8
WAITLOCK BPLCKC QLDIS CCDIS
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ONDEMAND RUNSTDBY USBCRM LLAW STABLE MODE ENABLE
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 1 0 0 0 0 0 0
Bit 11 – WAITLOCK Wait Lock
This bit controls the DFLL output clock, depending on lock status:
Value Description
0
Output clock before the DFLL is locked.
1
Output clock when DFLL is locked.
Bit 10 – BPLCKC Bypass Coarse Lock
This bit controls the coarse lock procedure:
Value Description
0
Bypass coarse lock is disabled.
1
Bypass coarse lock is enabled.
Bit 9 – QLDIS Quick Lock Disable
Value Description
0
Quick Lock is enabled.
1
Quick Lock is disabled.
Bit 8 – CCDIS Chill Cycle Disable
Value Description
0
Chill Cycle is enabled.
1
Chill Cycle is disabled.
Bit 7 – ONDEMAND On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral
clock requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the
oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the
oscillator s clock source, the oscillator will be in a disabled state.
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 222