Datasheet

17.8.4 Power and Clocks Status
Name: PCLKSR
Offset: 0x0C
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DPLLLTO DPLLLCKF
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 17 – DPLLLTO DPLL Lock Timeout
Value Description
0
DPLL Lock time-out not detected.
1
DPLL Lock time-out detected.
Bit 16 – DPLLLCKF DPLL Lock Fall
Value Description
0
DPLL Lock fall edge not detected.
1
DPLL Lock fall edge detected.
Bit 15 – DPLLLCKR DPLL Lock Rise
Value Description
0
DPLL Lock rise edge not detected.
1
DPLL Lock fall edge detected.
Bit 11 – B33SRDY BOD33 Synchronization Ready
Value Description
0
BOD33 synchronization is complete.
1
BOD33 synchronization is ongoing.
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 207