Datasheet

17.8.3 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x08
Reset: 0x00000000
Property: -
Note: Depending on the fuse settings, various bits of the INTFLAG register can be set to one at startup.
Therefore the user should clear those bits before using the corresponding interrupts.
Bit 31 30 29 28 27 26 25 24
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DPLLLTO DPLLLCKF
Access
R R R R R R R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DPLLLCKR B33SRDY BOD33DET BOD33RDY DFLLRCS
Access
R/W R R R R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DFLLLCKC DFLLLCKF DFLLOOB DFLLRDY OSC8MRDY OSC32KRDY XOSC32KRDY XOSCRDY
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 17 – DPLLLTO DPLL Lock Timeout
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Timeout bit in the Status register
(PCLKSR.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Timeout interrupt flag.
Bit 16 – DPLLLCKF DPLL Lock Fall
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Fall bit in the Status register
(PCLKSR.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Fall interrupt flag.
Bit 15 – DPLLLCKR DPLL Lock Rise
This flag is cleared by writing a one to it.
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 203