Datasheet

Bit 15 – DPLLLCKR DPLL Lock Rise Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock
Rise interrupt.
Value Description
0
The DPLL Lock Rise interrupt is disabled.
1
The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when
the DPLL Lock Rise Interrupt flag is set.
Bit 11 – B33SRDY BOD33 Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables
the BOD33 Synchronization Ready interrupt.
Value Description
0
The BOD33 Synchronization Ready interrupt is disabled.
1
The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be
generated when the BOD33 Synchronization Ready Interrupt flag is set.
Bit 10 – BOD33DET BOD33 Detection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33
Detection interrupt.
Value Description
0
The BOD33 Detection interrupt is disabled.
1
The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when
the BOD33 Detection Interrupt flag is set.
Bit 9 – BOD33RDY BOD33 Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33
Ready interrupt.
Value Description
0
The BOD33 Ready interrupt is disabled.
1
The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the
BOD33 Ready Interrupt flag is set.
Bit 8 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables
the DFLL Reference Clock Stopped interrupt.
Value Description
0
The DFLL Reference Clock Stopped interrupt is disabled.
1
The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be
generated when the DFLL Reference Clock Stopped Interrupt flag is set.
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 196