Datasheet

while DFLLRDY is zero will be ignored. An interrupt is generated on a zero-to-one transition of DFLLRDY

if the DFLLRDY bit (INTENSET.DFLLDY) in the Interrupt Enable Set register is set.

In order to read from any of the DFLL48M configuration registers, the user must request a read

synchronization by writing a one to DFLLSYNC.READREQ. The registers can be read only when

PCLKSR.DFLLRDY is set. If DFLLSYNC.READREQ is not written before a read, a synchronization will

be started, and the bus will be halted until the synchronization is complete. Reading the DFLL48M

registers when the DFLL48M is disabled will not halt the bus.

The prescaler counter used to trigger one-shot brown-out detections also operates asynchronously from

the peripheral bus. As a consequence, the prescaler registers require synchronization when written or

read. The synchronization results in a delay from when the initialization of the write or read operation

begins until the operation is complete.

The write-synchronization is triggered by a write to the BOD12 or BOD33 control register. The

Synchronization Ready bit (PCLKSR.B12SRDY or PCLKSR.B33SRDY) in the PCLKSR register will be

cleared when the write-synchronization starts and set when the write-synchronization is complete. When

the write-synchronization is ongoing (PCLKSR.B33SRDY or PCLKSR.B12SRDY is zero), an attempt to

do any of the following will cause the peripheral bus to stall until the synchronization is complete:

• Writing to the BOD33 or BOD12 control register

• Reading the BOD33 or BOD12 control register that was written

The user can either poll PCLKSR.B12SRDY or PCLKSR.B33SRDY or use the INTENSET.B12SRDY or

INTENSET.B33SRDY interrupts to check when the synchronization is complete. It is also possible to

perform the next read/write operation and wait, as this next operation will be completed after the ongoing

read/write operation is synchronized.

SAM D21 Family

SYSCTRL – System Controller

Datasheet Complete

DS40001882D-page 191